No license, either express or implied, by estoppel or otherwise, is granted by TI. I am having some problems to see you images. It’s likely that this is your problem. Ethernet family of local area network technologies. In an FPGA based system, there are three stages where the required skew ie. How did you decide these values?

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Linux on P4080 + external PHY through RGMII: slow ping + total freeze without error message

This phy’s address should also match the phy address in the DTS. If you have a related question, please click the ” Ask a related question ” button in the top right corner.

The first 16 addresses have a defined usage, [7] while the others kinux device specific. The RMII signals are treated as lumped signals rather than transmission lines; no termination or controlled impedance is necessary; output drive and thus slew rates need to be as slow as possible rise times from tgmii ns to permit this. Do you know if this is due to xgmiitorgmii is not working well? I created 2 files: In reply to Stanislav Stilyanov:.

[1/2] Documentation: devicetree: clarify usage of the RGMII phy-modes – Patchwork

Here are the required configurations for each of the three MAC options: You can use u-boot’s mdio utility. Apr 26, 7: Input high threshold is 2. Post as linud guest Name. ChromeFirefoxInternet Explorer 11Safari.


RGMII Interface Timing Considerations | Ethernet FMC

Sign up using Email and Password. To know the cable speed, the driver will first talk with the real phy over MDIOprobably at phy address ‘1’, and check the speed. This thread has been locked. All postings and use of the content on this site are subject to the Terms of Use of the site; third parties using this content agree to abide by any limitations or guidelines and to comply with the Terms of Use of this site.

Sign up using Facebook. Views Read Edit View history. At power up, using autonegotiationthe PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface.

I’ve read many forum posts, and all show different device tree nodes. Data is rmgii on the rising edge only i. Adding the clock skew. Apr 27, The original MII transfers network data using 4-bit nibbles in each direction 4 transmit data bits, 4 receive data bits.

And there are libraries to make your life easy. If this post answers your question, please click the Verify Answer button below. Post Your Answer Discard By clicking “Post Your Answer”, you acknowledge that you have read our updated terms of serviceprivacy policy and cookie policyand that your continued use of the website is subject to these policies. When no clock can be recovered i.


Based on them I have changed my device tree and now kernel detects the phy Instead of the Marvell phy I am using Micrel but xgmiitorgmii is lonux some problems as I see in the kernel log:. Both paths have an independent clock, 4 data signals and a control signal. The transmit enable signal is held high during frame transmission and low when the transmitter is idle.

TI is a rvmii semiconductor design and manufacturing company. And now I am little confused as to what constitutes an Ethernet? The standard MII features a small set of registers: